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12.4b Logic gates labs

Source: Lab ideas from Computational Physics (Landau, Páez, Bordeianu), §12.4. Classical NodeLab truth-table checks + pure-Python unitary locks. Continues 12.4.

Explorer​

Classical wiring (NodeLab)​

Half-adder sum again (AND + OR + NAND path optional)​

Build Y=A⊕BY=A\oplus B with XOR from the deck (or the AND/OR/NAND recipe from digital logic). Toggle inputs live; Check exhausts the truth table.

NOR as “neither”​

Y=A+B‾Y=\overline{A+B} — drag NOR, wire both inputs.

Wire Bell again (schema-style)​

Field-to-field: |00⟩ → H → CNOT → |β₀₀⟩. Same wiring checker as schema design.

Quantum unitaries (CodeExercise)​

Pure Python. No Cirq / Qiskit in the sandbox.

Formula refresh​

Warm up: pick the matching equation among lookalikes (same walk as the theory lesson).

Activity: H00=1/2H_{00}=1/\sqrt{2}

Print the top-left entry of the Hadamard matrix with 10 decimals.

No input.

Write-ups​

0/3 solved
12.4b.W1

Using “half”, “adder”, “xor”, and “and”, explain:

Which classical gates implement a half-adder’s sum and carry?

Minimum 3 words. Your answer must include: “half”, “adder”, “xor”, “and”.

0 words/ 3 min

Meet the writing requirements, then you can open the model answer.

Next: 12.5 Cirq / QC programming.